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Patent for Sale:

Five Transistor SRAM Cell Technique.    

Read-write Methods for a 5-transistor SRAM memory cell. The methods facilitate very low standby power.


Advanced CMOS technology is widely used to implement static random access memories. Five transistor memory cells have the potential for space and power savings but a single transistor access port presents read-write difficulties. This patent offers a combination of circuit techniques that improve read-write access performance as well as lower memory and bit line standby power.

Primary Application of the Technology

Embedded CMOS systems applications that are power and silicon area sensitive.

The Problem Solved by the Technology

Methods are presented for improving read-write techniques in a space saving five transistor CMOS SRAM memory cell. The methods also achieve very low standby power.

How the Technology Solves the Problem

Bit line standby voltage is not driven to a high (VDD) level as in other SRAM designs. In addition, a precharge operation is not necessary as the standby voltage is suitable for either a read or a write cycle.

Competitive Advantage

Addresses prior art drawbacks with new methods.

Patent Summary

U.S. Patent Classes & Classifications Covered in this listing:

Class 365: Static Information Storage And Retrieval

Apparatus or corresponding processes for the static storage and retrieval of information. For classification herein, the storage system must be (1) static, (2) a singular storage element or plural elements of the same type, (3) addressable.

Subclass 154: Flip-flop (electrical)

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