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Patent for Sale:

Hybrid Multicore Processor Architecture    

The invention is valuable to chipsets going in to mobile phones, smart mobile devices, data processing equipment, consumer electronics etc.

Overview

This portfolio is from a seasoned inventor with over 150 patents, his inventions have generated large IP revenue for a number of Fortune 100 companies. The inventor is an expert in multicore processing and memory design in mobile devices.

The patents will be of interest to companies looking to exploit the advantage of using mixed vendor technologies. The invention is valuable to chipsets going in to mobile phones, smart mobile devices, data processing equipment, consumer electronics etc. The invention would be a benefit to devices such as IPTV, set-top boxes, DTV and notebook PC.

The issued patent in this portfolio addresses a specific configuration having a unified data bus architecture, as well as an OS packet translator. The pending application addresses multiple cores that handle processing of data from a unified data bus. Combined, these patents form a solid foundation to new generation architectures leveraging many core capabilities, and can be applied to any multiple generic microprocessor architecture with a set of controlling components and a set of groups of sub-processing components. Under this arrangement, different vendor technology cores and function components, such as memory, are organized in a way that differing technologies are collaborating as a system.

Primary Application of the Technology

Multicore processor, inter-chipset, low power consumer electronics, mobile devices.

Competitive Advantage

- Vendor technology independent.
- Provides a core technology.
- Transparent for applications (e.g. media processing, codex, 3D, h.264).
- Transparent for different technology upgrade: platform continuity.
- Multiple vendor sources for manufacturing.
- Scalable performance.
- Low power – power saving (virtualization).
- Redundancy and higher chip yield (core virtualization).
- Reusability of codes.
- Stable product roadmap.
- Reduced development time and shorter time-to-market.

Patent Summary

U.S. Patent Classes & Classifications Covered in this listing:

Class 712: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (E.G., Processors)

This class provides, within a computer or digital data processing system, for subject matter represented by a particular arrangement that includes at least one of the following means: 1. components of an individual complete processor, which may be formed on a single integrated circuit (IC); 2. components of a complete digital data processing system; 3. plural processors; or 4. plural digital data processing systems; wherein the particular arrangement further includes at least one of the following functions: (a) processing instruction data for specific processor architectures; (b) accessing or retrieving instruction data of a fixed or variable length from a buffer or other memory and shifting the instruction data to align it with a physical boundary of a buffer or other memory; (c) locating and retrieving instruction data for processing; (d) determining via internal hardware, firmware or software operations the meaning of operation codes, control bits, or operands of instruction data; (e) dispatching instruction data for execution (e.g., designating a register after resolving data conflicts); (f) dynamically testing instruction data and operands to assess conflicts related to data or hardware-resource availability (e.g., identifying data dependencies or utilization conflicts, attempting to resolve such dependencies or conflicts, or both); and (g) dynamically controlling the execution, processing, or sequencing of instruction data within a processor.

Subclass 29: Interface
Subclass 32: Microprocessor or multichip or multimodule processor having sequential program control

Class 710: Electrical Computers And Digital Data Processing Systems: Input/Output

This class provides, within a computer or digital data processing system with the following processes or apparatus for 1. transferring data from one or more peripherals to one or more computers or digital data processing systems for the latter to process, store, or further transfer or for transferring data from the computers or digital data processing systems to the peripherals; 2. for interconnecting or communicating between two or more components connected to an interconnection medium (e.g., a bus) within a single computer or digital data processing system; 3. for preventing access to a shared resource of a computer or digital data processing system; 4. for granting access to a shared resource of a computer of digital data processing system by one of a plurality of components of the computer or digital data processing system by interrogating each of the components in a predetermined order; 5. for determining which of a plurality of components of a computer or digital data processing system contending for access to a shared resource shall be granted access at any one time based upon a predetermined criteria; and 6. for stopping, halting, or suspending a current processing function within a computer or digital data processing system.

Subclass 306: Bus bridge

Class 370: Multiplex Communications

This is the generic class for multiplexing or duplexing systems, methods, or apparatus.

Subclass 412: Queuing arrangement
Subclass 419: Input or output circuit, per se (i.e., line interface)

Class 711: Electrical Computers And Digital Processing Systems: Memory

This class provides, within an electrical computer or digital data processing system, for the following processes and apparatus 1. for addressing memory wherein the processes and apparatus involve significant address manipulating (e.g., combining, translating, or mapping and other techniques for formatting and modifying address data) and are combined with specific memory configurations or memory systems; 2. for accessing and controlling memory (e.g., transferring and modifying address data, selecting storage devices, scheduling access); and 3. for forming memory addresses (e.g., virtual memory addressing, address translating, translation-lookaside buffers (TLBs), boundary checking, and page mode).

Subclass 148: Plural shared memories
Subclass 152: Memory access blocking
Subclass 163: Access limiting
Subclass 202: Address mapping (e.g., conversion, translation)
Subclass 203: Virtual addressing

Class 1: