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Patent for Sale:

Integration of Flash, Dynamic RAM and Multiple Components on Single Chip    

The portfolio covers the CPU and memory hierarchy virtualization, low power memory and storage technologies.


A family of U.S. patents is offered designed for integration of memory, storage and other components on a single chip or computing platform.

As mobile devices have emerged as the principal focus of today’s technology industry, the usage time of mobile devices has concurrently become the most critical factor in mobile technology development. Power-saving (or low power) devices are the key critical factor in designing successful mobile devices.

The low power technology sector is emerging as a new business arena poised to explode. Shifts in power processor, memory and system architecture technologies are set to usher in a new era. Memory technology has not seen a significant advancement in many years, but the recent demand for instant information extraction and advanced analytics in big data have led to more powerful memory device designs. Thus, power consumption of digital systems and faster processing are increasingly becoming the most important design parameters in this area.

Memory dominant applications such as real-time 3D gaming, speech recognition and video image processing are also being advanced with portability in mind. Currently, most portable devices incorporate new memory designs to meet power constraints. It has been shown that power consumed during memory accesses accounts for a significant portion of the total power consumption in processors; thus, minimization of memory power usage is an important area of concern for today’s mobile device designers.

Patent Summary

U.S. Patent Classes & Classifications Covered in this listing:

Class 257: Active Solid-State Devices (E.G., Transistors, Solid-State Diodes)

This class provides for active solid-state electronic devices, that is, electronic devices or components that are made up primarily of solid materials, usually semiconductors, which operate by the movement of charge carriers - electrons or holes - which undergo energy level changes within the material and can modify an input voltage to achieve rectification, amplification, or switching action, and are not classified elsewhere.

Subclass 686: Stacked arrangement
Subclass E23.011: Internal lead connections, e.g., via connections, feedthrough structures (EPO)
Subclass E21.511: Mounting on insulating member provided with metallic leads, e.g., flip-chip mounting, conductive die mounting (EPO)

Class 438: Semiconductor Device Manufacturing: Process

This class provides for manufacturing a semiconductor containing a solid-state device for the following purposes: (a) conducting or modifying an electrical current, (b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy. Also operations involving: (1) coating a substrate with a semiconductive material, or (2) coating a semiconductive substrate or substrate containing a semiconductive region. It also provides for operations involving etching a semiconductive substrate or etching a substrate containing a semiconductive region. The class provides for packaging or treatment of packaged semiconductor.

Subclass 109: Stacked array (e.g., rectifier, etc.)

Class 711: Electrical Computers And Digital Processing Systems: Memory

This class provides, within an electrical computer or digital data processing system, for the following processes and apparatus 1. for addressing memory wherein the processes and apparatus involve significant address manipulating (e.g., combining, translating, or mapping and other techniques for formatting and modifying address data) and are combined with specific memory configurations or memory systems; 2. for accessing and controlling memory (e.g., transferring and modifying address data, selecting storage devices, scheduling access); and 3. for forming memory addresses (e.g., virtual memory addressing, address translating, translation-lookaside buffers (TLBs), boundary checking, and page mode).

Subclass 145: Access control bit

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