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Patent for Sale:

Silicon-on-insulator (SOI) Semiconductor Manufacturing Technology    

Technology for creating Silicon-on-Insulator (“SOI”) semiconductors that costs 1/10th of the cost of current SOI technologies.

Overview

Technology for creating Silicon-on-Insulator (“SOI”) semiconductors that costs 1/10th of the cost of current SOI technologies. This technology is packaged in the form of 2 issued US Patents and associated trade secrets. Consulting from lead inventor is also available.

Silicon-on-Insulator is a semiconductor wafer technology that produces higher performing, lower power devices than traditional bulk silicon techniques. SOI works by placing a thin, insulating layer between a thin layer of silicon and the silicon substrate. The insulating layer helps reduce the amount of electrical charge that the transistor has to move during a switching operation, thus making the transistor faster and allowing it to switch using less energy. SOI chips can be as much as 15 percent faster and use 20 percent less power than today's bulk complementary metal–oxide semiconductor (CMOS) based chips.

Primary Application of the Technology

The primary market is high density semiconductors, especially semiconductor manufacturing.

The Problem Solved by the Technology

Silicon-on-insulator (SOI), a semiconductor process technology available today in mass production, offers many advantages to chip designers over traditional generic CMOS:

• Speed: Exploiting the floating-body effect of an SOI transistor allows a current drive increase that directly translates to a significant speed improvement.

• Power: When using thin silicon, a near ideal sub-threshold slope can be achieved in SOI transistors.

• Latchup free: With SOI, devices are fully wrapped in an insulator, resulting in near latchup-free circuits.

• Radiation hardness: SOI provides a drastic improvement in rad-hard performance based on the reduction in exposed silicon volume.

• RF performance: The use of high-resistivity SOI substrates reduces crosstalk and enables the integration of high quality on chip inductors.

• High temperature compatibility: As junction leakage is significantly reduced, circuits operating up to 400°C have been reported.
• Smart power integration: With the insulation from the SOI stack, high-voltage devices (to 250 V) can be easily integrated without any increase in process complexity.

• Embedded memory integration: The SOI floating-body effect can be used to create an ultra-dense DRAM block. These memories offer up to twice the density of embedded DRAM and up to five times the density of SRAM, yet they're fast and consume very little power.

How the Technology Solves the Problem

The technology in this portfolio produces an insulating or barrier layer, commonly called Silicon-On-Insulator (SOI) for semiconductor devices. The insulating layer is created by depositing a layer of silicon and at least one additional element, such as oxygen, on a silicon substrate where the deposited layer and the epitaxial silicon layer is complete and without holes. Essentially, a superlattice of silicon and another element is created by Molecular Beam Epitaxy (MBE), Chemical Vapor Deposition (CVD) or other method on the semiconductor, creating an insulating layer. Alternatively, a monolayer of one or more elements, preferably comprising oxygen, is absorbed on a silicon substrate. Several insulating layers sandwiched between epitaxial silicon forms a barrier composite.

The inventors have discovered a way to deposit a structure consisting of a monolayer of absorbed oxygen which contains less oxygen than is contained in SiO2. Oxygen is first introduced by absorption onto a clean silicon surface at temperatures up to 700⁰C and high vacuum pressure (<10-6 torr). Because the absorption process cannot exceed one monolayer under these controlled conditions, the method serves as a self-limiting process, ensuring the thickness of oxide at a monolayer, which is less than the amount of oxygen required to make a monolayer of SiO2, thus allowing the continuation of the Si epitaxial growth. The present results were obtained by using standard MBE (Molecular Beam Epitaxy) monitored by RHEED (Reflection High Energy Electron Diffraction). The epitaxial silicon sandwiched between two absorbed mono-layers of oxygen forms a unit, which can be repeated to give a superlattice structure. The barrier structure shows a barrier height of 0.5 eV, which is more than sufficient for most electronic and optoelectronic devices at room temperature. Current voltage measurements show the existence of a barrier, surface Auger shows the presence of oxygen where expected, and high resolution X-TEM (cross section transmission electron microscopy) shows almost defect free Epitaxy beyond the barrier layer.

Competitive Advantage

As semiconductors have increased in speed and density, problems with current leakage have started to limit the capability to further shrink transistors. Semiconductor manufacturers are driven by the market to lower cost, increase speed and densities each year. One technique that has been identified in the International Technology Roadmap for Semiconductors (ITRS) roadmap is Silicon-on-Insulator technology. Several attempts to implement SOI in recent years have been mostly successful, but at a high manufacturing cost. A 12 inch wafer may cost $1150 with current SOI technology as opposed to $150 for bulk Silicon wafer. The proven technology in this offer reduces the cost of SOI by a factor of 10, adding only $100 to the cost of a bulk Silicon wafer ($250 overall cost).

The seller would like to be granted a license back.

The seller may consider selling these patents individually.

Additional Information

The inventor is available for an appropriate fee to assist the purchaser in the implementation of the technology.

Patent Summary

U.S. Patent Classes & Classifications Covered in this listing:

Class 438: Semiconductor Device Manufacturing: Process

This class provides for manufacturing a semiconductor containing a solid-state device for the following purposes: (a) conducting or modifying an electrical current, (b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy. Also operations involving: (1) coating a substrate with a semiconductive material, or (2) coating a semiconductive substrate or substrate containing a semiconductive region. It also provides for operations involving etching a semiconductive substrate or etching a substrate containing a semiconductive region. The class provides for packaging or treatment of packaged semiconductor.

Subclass 149: On insulating substrate or layer (e.g., TFT, etc.)
Subclass 404: Total dielectric isolation
Subclass 413: With epitaxial semiconductor formation
Subclass 478: FORMATION OF SEMICONDUCTIVE ACTIVE REGION ON ANY SUBSTRATE (E.G., FLUID GROWTH, DEPOSITION)
Subclass 479: On insulating substrate or layer
Subclass 787: Silicon oxide formation

Class 257: Active Solid-State Devices (E.G., Transistors, Solid-State Diodes)

This class provides for active solid-state electronic devices, that is, electronic devices or components that are made up primarily of solid materials, usually semiconductors, which operate by the movement of charge carriers - electrons or holes - which undergo energy level changes within the material and can modify an input voltage to achieve rectification, amplification, or switching action, and are not classified elsewhere.

Subclass 347: Single crystal semiconductor layer on insulating substrate (SOI)
Subclass 646: Coating of semi-insulating material (e.g., amorphous silicon or silicon-rich silicon oxide)
Subclass 649: Insulating layer of silicon nitride or silicon oxynitride
Subclass E21.566: Using lateral overgrowth technique, i.e., ELO techniques (EPO)
Subclass E21.567: Using bonding technique (EPO)