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Private Listing: Number 4333 Private  

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Patent Summary

U.S. Patent Classes & Classifications Covered in this listing:

Class 714: Error Detection/Correction And Fault Detection/Recovery

This class provides for process or apparatus for detecting and correcting errors in electrical pulse or pulse coded data; it also provides for process or apparatus for detecting and recovering from faults in electrical computers and digital data processing systems, as well as logic level based systems.

Subclass 763: Memory access
Subclass 766: Check bits stored in separate area of memory
Subclass 782: Bose-Chaudhuri-Hocquenghem code

Class 710: Electrical Computers And Digital Data Processing Systems: Input/Output

This class provides, within a computer or digital data processing system with the following processes or apparatus for 1. transferring data from one or more peripherals to one or more computers or digital data processing systems for the latter to process, store, or further transfer or for transferring data from the computers or digital data processing systems to the peripherals; 2. for interconnecting or communicating between two or more components connected to an interconnection medium (e.g., a bus) within a single computer or digital data processing system; 3. for preventing access to a shared resource of a computer or digital data processing system; 4. for granting access to a shared resource of a computer of digital data processing system by one of a plurality of components of the computer or digital data processing system by interrogating each of the components in a predetermined order; 5. for determining which of a plurality of components of a computer or digital data processing system contending for access to a shared resource shall be granted access at any one time based upon a predetermined criteria; and 6. for stopping, halting, or suspending a current processing function within a computer or digital data processing system.

Subclass 52: Input/Output data buffering
Subclass 53: Alternately filling or emptying buffers
Subclass 56: Buffer space allocation or deallocation

Class 711: Electrical Computers And Digital Processing Systems: Memory

This class provides, within an electrical computer or digital data processing system, for the following processes and apparatus 1. for addressing memory wherein the processes and apparatus involve significant address manipulating (e.g., combining, translating, or mapping and other techniques for formatting and modifying address data) and are combined with specific memory configurations or memory systems; 2. for accessing and controlling memory (e.g., transferring and modifying address data, selecting storage devices, scheduling access); and 3. for forming memory addresses (e.g., virtual memory addressing, address translating, translation-lookaside buffers (TLBs), boundary checking, and page mode).

Subclass 105: Dynamic random access memory
Subclass 117: Hierarchical memories
Subclass 119: Multiple caches
Subclass 122: Hierarchical caches
Subclass 154: Control technique
Subclass 158: Prioritizing
Subclass 167: Access timing