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Private Listing: Number 4093 Private  

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Patent Summary

U.S. Patent Classes & Classifications Covered in this listing:

Class 707: Data Processing:Database And File Management Or Data Structures

This is the generic class for data processing apparatus and corresponding methods for the retrieval of data stored in a database or as computer files. It provides for data processing means or steps for generic data, file and directory upkeeping, file naming, and file and database maintenance including integrity consideration, recovery, and versioning. There are three main divisions: 1. database and file accessing; 2. database schema and data structure; 3. file and database maintenance.

Subclass E17.01: File systems; file servers (EPO)
Subclass E17.011: Processing chained data, e.g., graphs, linked lists, etc. (EPO)

Class 711: Electrical Computers And Digital Processing Systems: Memory

This class provides, within an electrical computer or digital data processing system, for the following processes and apparatus 1. for addressing memory wherein the processes and apparatus involve significant address manipulating (e.g., combining, translating, or mapping and other techniques for formatting and modifying address data) and are combined with specific memory configurations or memory systems; 2. for accessing and controlling memory (e.g., transferring and modifying address data, selecting storage devices, scheduling access); and 3. for forming memory addresses (e.g., virtual memory addressing, address translating, translation-lookaside buffers (TLBs), boundary checking, and page mode).

Subclass 112: Direct access storage device (DASD)
Subclass 117: Hierarchical memories
Subclass 118: Caching
Subclass 125: Instruction data cache
Subclass 129: Partitioned cache
Subclass 140: Cache pipelining
Subclass 141: Coherency
Subclass 144: Cache status data bit
Subclass 145: Access control bit
Subclass 147: Shared memory area
Subclass 148: Plural shared memories
Subclass 154: Control technique
Subclass 167: Access timing
Subclass 169: Memory access pipelining
Subclass 202: Address mapping (e.g., conversion, translation)
Subclass 214: Operand address generation
Subclass 217: Generating a particular pattern/sequence of addresses
Subclass 220: Combining two or more values to create address

Class 715: Data Processing: Presentation Processing Of Document

This class provides for data processing means or steps wherein a) human perceptible elements of electronic information (i.e., text or graphics) are gathered, associated, created, formatted, edited, prepared, or otherwise processed in forming a unified collection of such information storable as a distinct entity, b) a users interaction with a computer system is used to control the presentation of display data; such interaction is interpreted and used by a data processor or computer architecture wherein system level elements of computation or data processing techniques are used prior to use with or in a specific display system, or c) a small program takes over a display screen if there are no keystrokes or mouse movements for a specified duration.


Class 710: Electrical Computers And Digital Data Processing Systems: Input/Output

This class provides, within a computer or digital data processing system with the following processes or apparatus for 1. transferring data from one or more peripherals to one or more computers or digital data processing systems for the latter to process, store, or further transfer or for transferring data from the computers or digital data processing systems to the peripherals; 2. for interconnecting or communicating between two or more components connected to an interconnection medium (e.g., a bus) within a single computer or digital data processing system; 3. for preventing access to a shared resource of a computer or digital data processing system; 4. for granting access to a shared resource of a computer of digital data processing system by one of a plurality of components of the computer or digital data processing system by interrogating each of the components in a predetermined order; 5. for determining which of a plurality of components of a computer or digital data processing system contending for access to a shared resource shall be granted access at any one time based upon a predetermined criteria; and 6. for stopping, halting, or suspending a current processing function within a computer or digital data processing system.

Subclass 310: Buffer or que control
Subclass 240: ACCESS ARBITRATING

Class 370: Multiplex Communications

This is the generic class for multiplexing or duplexing systems, methods, or apparatus.

Subclass 402: Bridge between bus systems

Class 709: Electrical Computers And Digital Processing Systems: Multicomputer Data Transferring

This class provides for an electrical computer or digital data processing system or corresponding data processing method including apparatus or steps for transferring data or instruction information between a plurality of computers wherein the computers employ the data or instructions before or after transferring and the employing affects said transfer of data or instruction information. The class includes - process or apparatus for transferring data among a plurality of spatially distributed (i.e., situated, at plural locations) computers or digital data processing systems via one or more communications media (e.g., computer networks).


Class 712: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (E.G., Processors)

This class provides, within a computer or digital data processing system, for subject matter represented by a particular arrangement that includes at least one of the following means: 1. components of an individual complete processor, which may be formed on a single integrated circuit (IC); 2. components of a complete digital data processing system; 3. plural processors; or 4. plural digital data processing systems; wherein the particular arrangement further includes at least one of the following functions: (a) processing instruction data for specific processor architectures; (b) accessing or retrieving instruction data of a fixed or variable length from a buffer or other memory and shifting the instruction data to align it with a physical boundary of a buffer or other memory; (c) locating and retrieving instruction data for processing; (d) determining via internal hardware, firmware or software operations the meaning of operation codes, control bits, or operands of instruction data; (e) dispatching instruction data for execution (e.g., designating a register after resolving data conflicts); (f) dynamically testing instruction data and operands to assess conflicts related to data or hardware-resource availability (e.g., identifying data dependencies or utilization conflicts, attempting to resolve such dependencies or conflicts, or both); and (g) dynamically controlling the execution, processing, or sequencing of instruction data within a processor.

Subclass 230: Generating next microinstruction address
Subclass E9.055: Instruction prefetch, e.g., instruction buffer (EPO)
Subclass E9.072: Decoding (EPO)