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Patent for Sale:

Memory Management    

Five U.S. patents offered for sale

Overview

The patent portfolio relates to memory management, in particular, they relate to write purge operations, resolving ambiguous invalidate messages, managing multiple requests, and ensuring the integrity of data movement operations from virtual memory.

Exemplary patent relates to the parallel accessing of memory modules for reading or writing when the accesses are not dependent on the completion of a previous access.

Patent Lot Citation(s):
This lot is forward referenced by the following companies: Apple, IBM, Intel, Nortel Networks, Sun Microsystems, and Texas Instruments.

Primary Application of the Technology

Memory

Patent Summary

U.S. Patent Classes & Classifications Covered in this listing:

Class 711: Electrical Computers And Digital Processing Systems: Memory

This class provides, within an electrical computer or digital data processing system, for the following processes and apparatus 1. for addressing memory wherein the processes and apparatus involve significant address manipulating (e.g., combining, translating, or mapping and other techniques for formatting and modifying address data) and are combined with specific memory configurations or memory systems; 2. for accessing and controlling memory (e.g., transferring and modifying address data, selecting storage devices, scheduling access); and 3. for forming memory addresses (e.g., virtual memory addressing, address translating, translation-lookaside buffers (TLBs), boundary checking, and page mode).

Subclass 5: For multiple memory modules (e.g., banks, interleaved memory)
Subclass 121: Private caches
Subclass 141: Coherency
Subclass 147: Shared memory area
Subclass 154: Control technique
Subclass 202: Address mapping (e.g., conversion, translation)

Class 710: Electrical Computers And Digital Data Processing Systems: Input/Output

This class provides, within a computer or digital data processing system with the following processes or apparatus for 1. transferring data from one or more peripherals to one or more computers or digital data processing systems for the latter to process, store, or further transfer or for transferring data from the computers or digital data processing systems to the peripherals; 2. for interconnecting or communicating between two or more components connected to an interconnection medium (e.g., a bus) within a single computer or digital data processing system; 3. for preventing access to a shared resource of a computer or digital data processing system; 4. for granting access to a shared resource of a computer of digital data processing system by one of a plurality of components of the computer or digital data processing system by interrogating each of the components in a predetermined order; 5. for determining which of a plurality of components of a computer or digital data processing system contending for access to a shared resource shall be granted access at any one time based upon a predetermined criteria; and 6. for stopping, halting, or suspending a current processing function within a computer or digital data processing system.

Subclass 22: Direct Memory Accessing (DMA)
Subclass 24: By command chaining
Subclass 60: Transfer rate regulation