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EDA Tools - VLIW    

Electronic design automation for very large instruction word processor design.


The portfolio relates to electronic design automation for very large instruction word processor design. In particular, they relate to programmable and non-programmable processors having Explicitly Parallel Instruction Computing Architectures (EPIC).

Exemplary Patent(s):
Generally relates to a programmatic system and method for exploring the design space of a VLIW computer, allowing system designers to evaluate many candidate processor designs in an automated fashion.

Patent Lot Citation(s):
This portfolio is forward referenced by the following companies: Altera, ARC International, CriticalBlue, IBM, Intergraph, Liga Systems, LSI Corporation, Motorola, NEC, Panasonic, Philips, Silicon Graphics, Tensilica, and Xilinx.

Primary Application of the Technology


Patent Summary

U.S. Patent Classes & Classifications Covered in this listing:

Class 716: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask

This class provides for electrical data processing apparatus and corresponding methods for the following subject matter: for sketching, designing, and analyzing circuit components; for planning, designing, analyzing, and devising a template used for etching circuit pattern on semiconductor wafers.

Subclass 17: Programmable integrated circuit (e.g., basic cell, standard cell, macrocell)
Subclass 18: Logical circuit synthesizer
Subclass 2: Optimization (e.g., redundancy, compaction)
Subclass 3: Translation (e.g., conversion, equivalence)

Class 717: Data Processing: Software Development, Installation, And Management

This class provides for software program development tool and techniques including processes and apparatus for controlling data processing operations pertaining to the development, maintenance, and installation of software programs. Such processes and apparatus include: processes and apparatus for program development functions such as specification, design, generation, and version management of source code programs; processes and apparatus for debugging of computer program including monitoring, simulation, emulation, and profiling of software programs; processes and apparatus for translating or compiling programs from a high-level representation to an intermediate code representation and finally into an object or machine code representation, including linking, and optimizing the program for subsequent execution; processes and apparatus for updating, installing, and version management of developed code.

Subclass 149: For a parallel or multiprocessor system

Class 712: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (E.G., Processors)

This class provides, within a computer or digital data processing system, for subject matter represented by a particular arrangement that includes at least one of the following means: 1. components of an individual complete processor, which may be formed on a single integrated circuit (IC); 2. components of a complete digital data processing system; 3. plural processors; or 4. plural digital data processing systems; wherein the particular arrangement further includes at least one of the following functions: (a) processing instruction data for specific processor architectures; (b) accessing or retrieving instruction data of a fixed or variable length from a buffer or other memory and shifting the instruction data to align it with a physical boundary of a buffer or other memory; (c) locating and retrieving instruction data for processing; (d) determining via internal hardware, firmware or software operations the meaning of operation codes, control bits, or operands of instruction data; (e) dispatching instruction data for execution (e.g., designating a register after resolving data conflicts); (f) dynamically testing instruction data and operands to assess conflicts related to data or hardware-resource availability (e.g., identifying data dependencies or utilization conflicts, attempting to resolve such dependencies or conflicts, or both); and (g) dynamically controlling the execution, processing, or sequencing of instruction data within a processor.

Subclass E9.028: Instruction analysis, e.g., decoding, instruction word fields (EPO)
Subclass E9.054: Of compound instructions (EPO)