Patent for Sale:

PCI and SCSI bus Technology    

Processor & Storage Systems

Overview

These inventions relate to fetching hints on PCI bus, synchronized node transmission, high data transfer rate asynchronous bus, SCSI bus arbitration controllers, and relaxed bus protocols.

The seller would like to be granted a license back.

The seller may consider selling these patents individually.

Patent Summary

U.S. Patent Classes & Classifications Covered in this listing:

Class 710: Electrical Computers And Digital Data Processing Systems: Input/Output

This class provides, within a computer or digital data processing system with the following processes or apparatus for 1. transferring data from one or more peripherals to one or more computers or digital data processing systems for the latter to process, store, or further transfer or for transferring data from the computers or digital data processing systems to the peripherals; 2. for interconnecting or communicating between two or more components connected to an interconnection medium (e.g., a bus) within a single computer or digital data processing system; 3. for preventing access to a shared resource of a computer or digital data processing system; 4. for granting access to a shared resource of a computer of digital data processing system by one of a plurality of components of the computer or digital data processing system by interrogating each of the components in a predetermined order; 5. for determining which of a plurality of components of a computer or digital data processing system contending for access to a shared resource shall be granted access at any one time based upon a predetermined criteria; and 6. for stopping, halting, or suspending a current processing function within a computer or digital data processing system.

Subclass 22: Direct Memory Accessing (DMA)
Subclass 35: Burst data transfer
Subclass 36: Input/Output access regulation
Subclass 62: Peripheral adapting
Subclass 100: INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING)
Subclass 105: Protocol
Subclass 106: Using transmitter and receiver
Subclass 107: Bus access regulation
Subclass 111: Rotational prioritizing (i.e., round robin)
Subclass 113: Centralized bus arbitration
Subclass 119: Decentralized bus arbitration
Subclass 123: Dynamic bus prioritization
Subclass 312: Multiple bridges
Subclass 240: ACCESS ARBITRATING
Subclass 244: Access prioritizing

Class 370: Multiplex Communications

This is the generic class for multiplexing or duplexing systems, methods, or apparatus.

Subclass 462: Arbitration for access to a channel

Class 714: Error Detection/Correction And Fault Detection/Recovery

This class provides for process or apparatus for detecting and correcting errors in electrical pulse or pulse coded data; it also provides for process or apparatus for detecting and recovering from faults in electrical computers and digital data processing systems, as well as logic level based systems.

Subclass 48: Error detection or notification
Subclass 701: Data formatting to improve error detection correction capability
Subclass 775: Synchronization
Subclass 798: Error detection for synchronization control

Class 711: Electrical Computers And Digital Processing Systems: Memory

This class provides, within an electrical computer or digital data processing system, for the following processes and apparatus 1. for addressing memory wherein the processes and apparatus involve significant address manipulating (e.g., combining, translating, or mapping and other techniques for formatting and modifying address data) and are combined with specific memory configurations or memory systems; 2. for accessing and controlling memory (e.g., transferring and modifying address data, selecting storage devices, scheduling access); and 3. for forming memory addresses (e.g., virtual memory addressing, address translating, translation-lookaside buffers (TLBs), boundary checking, and page mode).

Subclass 131: Multiport cache
Subclass 137: Look-ahead
Subclass 146: Snooping