Tynax ~ Patent Library

Patent Portfolio for Sale:

Memory & IC Devices & Fabrication    

Semiconductor memory & other integrated circuit devices & fabrication


US patents relating to semiconductor memory & other integrated circuit devices & fabrication. Inventions include:

* Polysilicon Resisitors
* Self aligned structures
* Interconnect
* etc

The seller would like to be granted a license back.

Patent Summary

U.S. Patent Classes & Classifications Covered in this Patent Portfolio:

Class 257: Active Solid-State Devices (E.G., Transistors, Solid-State Diodes)

This class provides for active solid-state electronic devices, that is, electronic devices or components that are made up primarily of solid materials, usually semiconductors, which operate by the movement of charge carriers - electrons or holes - which undergo energy level changes within the material and can modify an input voltage to achieve rectification, amplification, or switching action, and are not classified elsewhere.

Subclass 393: Insulated gate field effect transistor adapted to function as load element for switching insulated gate field effect transistor
Subclass 387: Gate electrode overlaps at least one of source or drain by no more than depth of source or drain (e.g., self-aligned gate)
Subclass 385: Multiple polysilicon layers
Subclass 384: Including silicide
Subclass 383: Contact of refractory or platinum group metal (e.g., molybdenum, tungsten, or titanium)
Subclass 382: With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide)
Subclass 381: With multiple levels of polycrystalline silicon
Subclass 380: Polysilicon resistor
Subclass 377: With polysilicon interconnections to source or drain regions (e.g., polysilicon laminated with silicide)
Subclass 368: Insulated gate field effect transistor in integrated circuit
Subclass E21.507: Formation of contacts to semiconductor by use of metal layers separated by insulating layers, e.g., self-aligned contacts to source/drain or emitter/base (EPO)
Subclass E21.414: Lateral single gate single channel transistor with inverted structure, i.e., channel layer is formed after gate (EPO)
Subclass E21.244: Involving dielectric removal step (EPO)
Subclass 776: Cross-over arrangement, component or structure
Subclass 774: Via (interconnection hole) shape
Subclass 773: Of specified configuration
Subclass 768: Refractory or platinum group metal or alloy or silicide thereof
Subclass 767: Resistive to electromigration or diffusion of the contact or lead material
Subclass 760: Separating insulating layer is laminate or composite of plural insulating materials (e.g., silicon oxide on silicon nitride, silicon oxynitride)
Subclass 758: Multiple metal levels on semiconductor, separated by insulating layer (e.g., multiple level metallization for integrated circuit)
Subclass 754: At least one layer of silicide or polycrystalline silicon
Subclass 644: At least one layer of glass
Subclass 635: Multiple layers
Subclass 536: Including resistive element
Subclass 401: With specified physical layout (e.g., ring gate, source/drain regions shared between plural FETs, plural sections connected in parallel to form power MOSFET)
Subclass E27.098: Static random access memory, SRAM, structure (EPO)
Subclass E27.099: Load element being a MOSFET transistor (EPO)
Subclass E27.1: Load element being a thin film transistor (EPO)
Subclass E27.101: Load element being a resistor (EPO)
Subclass E21.575: Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (EPO)
Subclass E21.59: Local interconnects; local pads (EPO)
Subclass E21.602: To produce devices each consisting of plurality of components, e.g., integrated circuits (EPO)
Subclass E21.64: With particular manufacturing method of gate sidewall spacers, e.g., double spacers, particular spacer material or shape (EPO)
Subclass E21.641: Interconnection or wiring or contact manufacturing related aspects (EPO)
Subclass E21.661: Static random access memory structures (SRAM) (EPO)
Subclass E23.151: Geometry or layout of interconnection structure (EPO)
Subclass E23.163: Principal metal being refractory metal (EPO)
Subclass E23.164: Containing semiconductor material, e.g., polysilicon (EPO)
Subclass E23.167: Insulating materials (EPO)
Subclass E29.278: With LDD structure or extension or offset region or characterized by doping profile (EPO)
Subclass E29.279: Asymmetrical source and drain regions (EPO)

Class 365: Static Information Storage And Retrieval

Apparatus or corresponding processes for the static storage and retrieval of information. For classification herein, the storage system must be (1) static, (2) a singular storage element or plural elements of the same type, (3) addressable.

Subclass 239: Sequential
Subclass 236: Counting
Subclass 230.08: Including particular address buffer or latch circuit arrangement
Subclass 230.06: Particular decoder or driver circuit
Subclass 221: Serial read/write
Subclass 194: Delay
Subclass 189.07: Including signal comparison
Subclass 189.05: Having particular data buffer or latch
Subclass 189.02: Multiplexing
Subclass 188: Four or more devices per bit
Subclass 182: Insulated gate devices
Subclass 154: Flip-flop (electrical)

Class 438: Semiconductor Device Manufacturing: Process

This class provides for manufacturing a semiconductor containing a solid-state device for the following purposes: (a) conducting or modifying an electrical current, (b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy. Also operations involving: (1) coating a substrate with a semiconductive material, or (2) coating a semiconductive substrate or substrate containing a semiconductive region. It also provides for operations involving etching a semiconductive substrate or etching a substrate containing a semiconductive region. The class provides for packaging or treatment of packaged semiconductor.

Subclass 384: Deposited thin film resistor
Subclass 303: Utilizing gate sidewall structure
Subclass 301: Source or drain doping
Subclass 233: And contact formation
Subclass 230: Utilizing gate sidewall structure
Subclass 163: Adjusting channel dimension (e.g., providing lightly doped source or drain region, etc.)
Subclass 152: Combined with electrical device not on insulating substrate or layer
Subclass 699: Plural coating steps
Subclass 698: Utilizing reflow
Subclass 586: Combined with formation of ohmic contact to semiconductor region
Subclass 529: Using same conductivity-type dopant
Subclass 517: Of semiconductor layer on insulating substrate or layer
Subclass 647: Having electrically conductive polysilicon component
Subclass 643: At least one layer forms a diffusion barrier

Class 148: Metal Treatment

Treating metal to modify or maintain the internal physical structure or chemical properties of metal. Most processes in this class relate to treating solid or semisolid metal with heat, without melting a substantial portion thereof, and also includes the combination of significant heating and working not provided for in other metal working classes. Cooling of metal to produce microstructure change is proper for this class. It includes processes of treating metal to intentionally develop, improve, modify, or preserve the magnetic properties of a free metal or alloy, occurring alone or mixed with one or more components. Also included are processes of reactive coating of metal wherein an externally supplied carburizing or nitriding agent is combined with the metal substrate to produce a carburized or nitridized or carbonitrided coating thereon or a uniformly carburized, nitrided, or carbonitrided metal alloy containing a metal element from said substrate.

Class 327: Miscellaneous Active Electrical Nonlinear Devices, Circuits, And Systems

This is the residual class for electrical devices, circuits or systems having an output not directly proportional to its input and comprising at least one component which can provide gain or can route electrical current and which device, circuit or system does not form a complete system such as is classified specifically elsewhere or a subcombination of utility only in such elsewhere classified system.

Subclass 264: Having specific active circuit element or structure (e.g., FET, complementary transistors, etc.)
Subclass 261: Having specific delay in producing output waveform