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Class 710: Electrical Computers And Digital Data Processing Systems: Input/Output

This class provides, within a computer or digital data processing system with the following processes or apparatus for 1. transferring data from one or more peripherals to one or more computers or digital data processing systems for the latter to process, store, or further transfer or for transferring data from the computers or digital data processing systems to the peripherals; 2. for interconnecting or communicating between two or more components connected to an interconnection medium (e.g., a bus) within a single computer or digital data processing system; 3. for preventing access to a shared resource of a computer or digital data processing system; 4. for granting access to a shared resource of a computer of digital data processing system by one of a plurality of components of the computer or digital data processing system by interrogating each of the components in a predetermined order; 5. for determining which of a plurality of components of a computer or digital data processing system contending for access to a shared resource shall be granted access at any one time based upon a predetermined criteria; and 6. for stopping, halting, or suspending a current processing function within a computer or digital data processing system.

Subclass 1: INPUT/OUTPUT DATA PROCESSING
Subclass 19: Status updating
Subclass 30: Frame forming
Subclass 33: Data transfer specifying
Subclass 40: Access prioritization
Subclass 52: Input/Output data buffering
Subclass 107: Bus access regulation
Subclass 240: ACCESS ARBITRATING
Subclass 243: Hierarchical or multilevel arbitrating

Class 370: Multiplex Communications

This is the generic class for multiplexing or duplexing systems, methods, or apparatus.

Subclass 236: Including signaling between network elements
Subclass 254: NETWORK CONFIGURATION DETERMINATION
Subclass 258: In a ring system
Subclass 403: At least one bus is a ring network
Subclass 404: Ring or loop forms backbone for interconnecting other networks
Subclass 458: Using time slots
Subclass 462: Arbitration for access to a channel
Subclass 468: Assignment of variable bandwidth or time period for transmission or reception
Subclass 506: Frame or bit stream justification

Class 711: Electrical Computers And Digital Processing Systems: Memory

This class provides, within an electrical computer or digital data processing system, for the following processes and apparatus 1. for addressing memory wherein the processes and apparatus involve significant address manipulating (e.g., combining, translating, or mapping and other techniques for formatting and modifying address data) and are combined with specific memory configurations or memory systems; 2. for accessing and controlling memory (e.g., transferring and modifying address data, selecting storage devices, scheduling access); and 3. for forming memory addresses (e.g., virtual memory addressing, address translating, translation-lookaside buffers (TLBs), boundary checking, and page mode).

Subclass 100: STORAGE ACCESSING AND CONTROL
Subclass 131: Multiport cache
Subclass 137: Look-ahead
Subclass 141: Coherency
Subclass 143: Write-back
Subclass 146: Snooping
Subclass 147: Shared memory area
Subclass 148: Plural shared memories
Subclass 150: Simultaneous access regulation
Subclass 151: Prioritized access regulation
Subclass 152: Memory access blocking
Subclass 204: Predicting, look-ahead
Subclass 213: Generating prefetch, look-ahead, jump, or predictive address

Class 712: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (E.G., Processors)

This class provides, within a computer or digital data processing system, for subject matter represented by a particular arrangement that includes at least one of the following means: 1. components of an individual complete processor, which may be formed on a single integrated circuit (IC); 2. components of a complete digital data processing system; 3. plural processors; or 4. plural digital data processing systems; wherein the particular arrangement further includes at least one of the following functions: (a) processing instruction data for specific processor architectures; (b) accessing or retrieving instruction data of a fixed or variable length from a buffer or other memory and shifting the instruction data to align it with a physical boundary of a buffer or other memory; (c) locating and retrieving instruction data for processing; (d) determining via internal hardware, firmware or software operations the meaning of operation codes, control bits, or operands of instruction data; (e) dispatching instruction data for execution (e.g., designating a register after resolving data conflicts); (f) dynamically testing instruction data and operands to assess conflicts related to data or hardware-resource availability (e.g., identifying data dependencies or utilization conflicts, attempting to resolve such dependencies or conflicts, or both); and (g) dynamically controlling the execution, processing, or sequencing of instruction data within a processor.

Subclass 2: Vector processor
Subclass 4: Distributing of vector data to vector registers
Subclass 7: Vector processor operation
Subclass 11: Array processor element interconnection
Subclass 15: Reconfiguring
Subclass 16: Array processor operation
Subclass 23: Superscalar
Subclass 26: Detection/pairing based on destination, ID tag, or data
Subclass 28: Distributed processing system
Subclass 29: Interface
Subclass E9.032: For specific instructions not covered by the preceding groups, e.g., halt, synchronize (EPO)
Subclass E9.046: Data or operand accessing, e.g., operand prefetch, operand bypass (EPO)
Subclass E9.049: Instruction issuing, e.g., dynamic instruction scheduling, out of order instruction execution (EPO)

Class 714: Error Detection/Correction And Fault Detection/Recovery

This class provides for process or apparatus for detecting and correcting errors in electrical pulse or pulse coded data; it also provides for process or apparatus for detecting and recovering from faults in electrical computers and digital data processing systems, as well as logic level based systems.

Subclass 10: Of processor
Subclass 11: Concurrent, redundantly operating processors
Subclass 22: With power supply status monitoring

Class 709: Electrical Computers And Digital Processing Systems: Multicomputer Data Transferring

This class provides for an electrical computer or digital data processing system or corresponding data processing method including apparatus or steps for transferring data or instruction information between a plurality of computers wherein the computers employ the data or instructions before or after transferring and the employing affects said transfer of data or instruction information. The class includes - process or apparatus for transferring data among a plurality of spatially distributed (i.e., situated, at plural locations) computers or digital data processing systems via one or more communications media (e.g., computer networks).

Subclass 200: Particular function performed
Subclass 232: Array of elements (e.g., AND/OR array, etc.)
Subclass 251: Oscillator controlled

Class 345: Computer Graphics Processing And Selective Visual Display Systems

Processes and apparatus for selective electrical control of two or more light-generating or light-controlling display elements* in accordance with a received or stored image data signal. The image data includes character, graphical information or display attribute data. The image data may include, for example, information data from a peripheral input device, from the reception of a television signal, from the recognition of image data, or from the generation or creation of image data by a computer.

Subclass 541: Shared memory
Subclass 556: For storing condition code, flag or status
Subclass 563: Mask data operation

Class 700: Data Processing: Generic Control Systems Or Specific Applications

This class is structured into two main divisions: (1)for the combination of a data processing or calculating computer apparatus (or corresponding methods for performing data processing or calculating operations) AND a device or apparatus controlled thereby, the entirety hereinafter referred to as a "control system". (2)for data processing or calculating computer apparatus (or corresponding methods for performing data processing or calculating operations) wherein the data processing or calculating computer apparatus is designed for or utilized in a particular art device, system, process, or environment, or is utilized for the solution of a particular problem in a field other than mathematics (arithmetic processing per se is classified elsewhere).

Subclass 2: Plural processors
Subclass 4: Parallel

Class 713: Electrical Computers And Digital Processing Systems: Support

This class provides, within a computer or digital data processing system, for the following processes or apparatus for: 1. establishing original operating parameters or data for a computer or digital data processing system, such as, allocating extended or expanded memory, specifying device drivers, paths, files, buffers, disk management, etc.; 2. for changing system settings or operational modes in a computer or digital data processing system after they have been set; 3. for increasing a system’s extension of protection of system hardware,software, or data frm maliciously caused destruction, unauthorized modification, or unauthorized disclosure; 4. for modifying or responding to the available power to a computer or digital data processing system or programmable calculator; 5. for synchronization of two or more processors; 6. wherein a clock or timing signals, timing pulses, or data associated with the control or regulation of any one or combination of processing components, memory components, and peripheral components are caused to operate in synchronization; 7. for generation, division, or distribution of clock signals, pulse signals, or timing signals in a computer or digital data processing system from one or more sources into groups of continuous and successive time increments, and including event timing and counting, and the correction of the clock signals, pulse signals, or timing signals; 8. wherein there is a significant temporal, incremental or sequencing control provided to one or more computers, digital data processing systems, processors, memory, or peripherals, or to data transmission between these systems or components.

Subclass 375: SYNCHRONIZATION OF PLURAL PROCESSORS
Subclass 400: SYNCHRONIZATION OF CLOCK OR TIMING SIGNALS, DATA, OR PULSES
Subclass 600: CLOCK CONTROL OF DATA PROCESSING SYSTEM, COMPONENT, OR DATA TRANSMISSION