Patent for Sale

Stacked System in Package Integrated Circuit

3D stacked package active passive integration provides high bandwidth DC-DC voltage conversion and low footprint.

Overview

Stacked Active Passive Integration (SAPI) reduces footprint area and saves valuable real-estate, components and cost in portables and small system in package assemblies. Minimizing parasitic elements in integrated assemblies, performance is significantly enhanced, such as in high bandwidth DC-DC point of load (POL) regulators in a microprocessor or portable electronic device assembly. Applications include DC-DC converters and regulators for cell phones and other portable electronics, microprocessor packages and transient noise and high-frequency switching voltage regulators.

Problem Solved by the Technology

Technology scaling for integrated circuits demands higher performance at lower cost and smaller form factors. Footprint and cost reduction simultaneous with higher performance is a key industry requirement. Co-packaged active and passive devices reduce footprint area to an extent, but require footprint that is the sum of footprint areas of the active device and the capacitance passive device typically co-packaged. Planar co-packaging is also associated with parasitic components in circuit pathways that limit performance, such as frequency and bandwidth in point of load switching regulators that may be employed for micro voltage domains in a compact electronic assembly. ComLSI’s Stacked Active Passive Integration provides footprint matching that of the capacitor while providing active circuit integration and functionality unhindered by pathway parasitic elements. Designs such as Transient Regulation and/or Active Noise Regulation are enabled and rendered low cost by this technology.

How the Technology Solves the Problem

The SAPI or Active Packaging architecture stacks an integrated circuit with a passive component such as a high-performance capacitor on a package that conforms to the form factor of the capacitor device. Hence the technology renders a passive capacitor into an “active capacitor� without changing its footprint on a system board or a package substrate while eliminating parasitic elements in circuit pathways between the active device (chip) and the capacitor. This assembly of an active device and a capacitor is then stacked onto another active device that is a load component. This is the closest physical and electrical assembly of a point of load voltage regulator or other electronic circuit assembly with a load component. This packaging architecture utilizes available space in the vertical dimension while enabling symbiotic functionality in, for example, heat conduction.

Primary Application of the Technology

All POL (point of load) voltage regulator applications in cell phones and other miniature electronic assemblies. Transient Regulators or Active Noise Regulators and Local Voltage Regulators for voltage domains in a microprocessor or other high performance, low energy and power VLSI assemblies.  

Other Potential Applications